The present invention relates to a data driven information processor, which performs image processing, arithmetic processing and so forth.
In a conventional Neumann-type computer, various commands are stored in a program memory as programs in advance. The program counter sequentially specifies addresses in the program memory to read these commands successively, and the read commands are executed.
On the other hand, a data driven information processor is a kind of a non-Neumann-type computer, which does not have a concept of sequential execution of commands by the program counter. Such a data driven information processor adopts an architecture wherein commands are processed in parallel. In this data driven information processor, commands can be executed as soon as all data to be processed are prepared. Then, since a plurality of commands are simultaneously driven by the prepared data, programs are executed in parallel along a spontaneous data flow. Therefore, it is considered that time required for operation is significantly reduced.
FIG. 5 is a block diagram showing an example of a configuration of a conventional data driven information processor. FIG. 6 shows an example of a field configuration in a data packet processed by the data driven information processor shown in FIG. 5.
The data packet shown in FIG. 6 includes a destination field, a command field and a data field. The destination field stores data memory information and node information, the command field stores command information and the data field stores operand data. Here, the data memory information is information used to specify an address in a data memory 6 shown in FIG. 5. The node information is information used to specify an address when a data flow program is read.
In FIG. 5, the data driven information processor includes an input/output control unit 1, program storage unit 2, pair data detection unit 3, arithmetic processing unit 4, data memory interface unit 5 and data memory 6.
The input/output control unit 1 has an input control function for merging data packets inputted from the outside or the like and sending them successively in order and an output control function for outputting data packets inputted from the arithmetic processing unit 4 to destinations according to provided destination information.
The program storage unit 2 stores a data flow program as shown in FIG. 7. The program storage unit 2 reads a pair of destination information 7 and command information 8 from the data flow program by address specification based on node information in the destination field of the data packet inputted from the input/output control unit 1. Then, the informations are stored in the destination field and the command field of the data packet, and the data packet is outputted to the pair data detection unit 3. It is noted that command information 8 includes information for the arithmetic processing unit 4 and information for the data memory interface unit 5.
The pair data detection unit 3 queues data packets inputted from the program storage unit 2. That is, the pair data detection unit 3 detects two data packets having the same destination information. Then, after operand data (contents of the data field) of one data packet is added into the data field of the other data packet, the other data packet is outputted. The arithmetic processing unit 4 executes an operation based on command information in the data packet inputted from the pair data detection unit 3, stores the result in the data field of the data packet and outputs the data packet to the input/output control unit 1.
The data memory interface unit 5 reads/writes data from/to the data memory 6 based on command information in the data packet inputted from the input/output control unit 1. As a result, contents of the data field of the data packet are stored in the data memory 6. It is noted that data memory information in the destination field of the data packet is used to specify an address in the data memory 6 by the data memory interface unit 5 at this time.
However, the conventional data driven information processor has the following problems. That is, when a data packet is inputted in the input/output control unit 1 from the outside, the data driven information processor executes an operation based on command information in this data packet or reads/writes data from/to the data memory 6. Therefore, input of a data packet from the outside is always necessary, and the data packet is processed depending on an outside clock.
In a Neumann-type computer, program commands are sequentially executed by a program counter operated in a fundamental frequency. However, since a data driven information processor does not have a concept of sequential execution of commands by the program counter, a plurality of commands are simultaneously driven by data, and programs are executed in parallel along a spontaneous data flow. Therefore, the operation rate depends on performance of LSI (Large-scale Integrated Circuits) such as processing or the like.
However, some programs need to be internally processed in a constant frequency different from an input frequency of a data packet from the outside. For example, there is a case where original picture data to be processed is already stored in the data memory 6 in image processing, and arithmetic processing can be performed only in a data driven information processor.
However, as described above, since a data packet is processed depending on an outside clock in the conventional data driven information processor even in such a case, a problem arises that the data cannot be processed when an input frequency of a data packet from the outside is too much faster than the processing frequency of the original picture data. On the contrary, when the input frequency of the data packet from the outside is slower than the processing frequency, the operation rate becomes unnecessarily low.